Pin Configuration

Pinout table

The M.2 M-key Stack FMC has a high pin count FPGA Mezzanine Card (FMC) connector, providing the connections to the FPGA on the development board. The following table defines the pinout of the FMC connector and describes each pin’s purpose on this mezzanine card.

To avoid confusion, we have chosen not to label the PCIe lanes as being TX or RX; instead we have labelled them with the direction in which the signal flows (eg. FPGA-to-SSD1 means that the FPGA transmits this signal and the SSD1 receives).

The last column of the table identifies all of the pins that are routed through to the Carrier-side FMC connector for use by the second mezzanine card. A cross (x) mark in this column indicates that the second mezzanine card can consider this pin floating (not connected).

PinPin nameNetDescriptionPassed through
A1GNDGNDGround✔️
A2DP1_M2C_PSSDA2FPGA_1_PPCIe lane 1 positive (SSD1-to-FPGA)
A3DP1_M2C_NSSDA2FPGA_1_NPCIe lane 1 negative (SSD1-to-FPGA)
A4GNDGNDGround✔️
A5GNDGNDGround✔️
A6DP2_M2C_PSSDA2FPGA_2_PPCIe lane 2 positive (SSD1-to-FPGA)
A7DP2_M2C_NSSDA2FPGA_2_NPCIe lane 2 negative (SSD1-to-FPGA)
A8GNDGNDGround✔️
A9GNDGNDGround✔️
A10DP3_M2C_PSSDA2FPGA_3_PPCIe lane 3 positive (SSD1-to-FPGA)
A11DP3_M2C_NSSDA2FPGA_3_NPCIe lane 3 negative (SSD1-to-FPGA)
A12GNDGNDGround✔️
A13GNDGNDGround✔️
A14DP4_M2C_PSSDB2FPGA_0_PPCIe lane 0 positive (SSD2-to-FPGA)
A15DP4_M2C_NSSDB2FPGA_0_NPCIe lane 0 negative (SSD2-to-FPGA)
A16GNDGNDGround✔️
A17GNDGNDGround✔️
A18DP5_M2C_PSSDB2FPGA_1_PPCIe lane 1 positive (SSD2-to-FPGA)
A19DP5_M2C_NSSDB2FPGA_1_NPCIe lane 1 negative (SSD2-to-FPGA)
A20GNDGNDGround✔️
A21GNDGNDGround✔️
A22DP1_C2M_PFPGA2SSDA_1_PPCIe lane 1 positive (FPGA-to-SSD1)
A23DP1_C2M_NFPGA2SSDA_1_NPCIe lane 1 negative (FPGA-to-SSD1)
A24GNDGNDGround✔️
A25GNDGNDGround✔️
A26DP2_C2M_PFPGA2SSDA_2_PPCIe lane 2 positive (FPGA-to-SSD1)
A27DP2_C2M_NFPGA2SSDA_2_NPCIe lane 2 negative (FPGA-to-SSD1)
A28GNDGNDGround✔️
A29GNDGNDGround✔️
A30DP3_C2M_PFPGA2SSDA_3_PPCIe lane 3 positive (FPGA-to-SSD1)
A31DP3_C2M_NFPGA2SSDA_3_NPCIe lane 3 negative (FPGA-to-SSD1)
A32GNDGNDGround✔️
A33GNDGNDGround✔️
A34DP4_C2M_PFPGA2SSDB_0_PPCIe lane 0 positive (FPGA-to-SSD2)
A35DP4_C2M_NFPGA2SSDB_0_NPCIe lane 0 negative (FPGA-to-SSD2)
A36GNDGNDGround✔️
A37GNDGNDGround✔️
A38DP5_C2M_PFPGA2SSDB_1_PPCIe lane 1 positive (FPGA-to-SSD2)
A39DP5_C2M_NFPGA2SSDB_1_NPCIe lane 1 negative (FPGA-to-SSD2)
A40GNDGNDGround✔️
B1CLK_DIRN/CPassed through✔️
B2GNDGNDGround✔️
B3GNDGNDGround✔️
B4DP9_M2C_PN/CNot connected
B5DP9_M2C_NN/CNot connected
B6GNDGNDGround✔️
B7GNDGNDGround✔️
B8DP8_M2C_PN/CNot connected
B9DP8_M2C_NN/CNot connected
B10GNDGNDGround✔️
B11GNDGNDGround✔️
B12DP7_M2C_PSSDB2FPGA_3_PPCIe lane 3 positive (SSD2-to-FPGA)
B13DP7_M2C_NSSDB2FPGA_3_NPCIe lane 3 negative (SSD2-to-FPGA)
B14GNDGNDGround✔️
B15GNDGNDGround✔️
B16DP6_M2C_PSSDB2FPGA_2_PPCIe lane 2 positive (SSD2-to-FPGA)
B17DP6_M2C_NSSDB2FPGA_2_NPCIe lane 2 negative (SSD2-to-FPGA)
B18GNDGNDGround✔️
B19GNDGNDGround✔️
B20GBTCLK1_M2C_PREFCLKB_FPGA_P100MHz PCIe reference clock for the FPGA
B21GBTCLK1_M2C_NREFCLKB_FPGA_N100MHz PCIe reference clock for the FPGA
B22GNDGNDGround✔️
B23GNDGNDGround✔️
B24DP9_C2M_PN/CNot connected
B25DP9_C2M_NN/CNot connected
B26GNDGNDGround✔️
B27GNDGNDGround✔️
B28DP8_C2M_PN/CNot connected
B29DP8_C2M_NN/CNot connected
B30GNDGNDGround✔️
B31GNDGNDGround✔️
B32DP7_C2M_PFPGA2SSDB_3_PPCIe lane 3 positive (FPGA-to-SSD2)
B33DP7_C2M_NFPGA2SSDB_3_NPCIe lane 3 negative (FPGA-to-SSD2)
B34GNDGNDGround✔️
B35GNDGNDGround✔️
B36DP6_C2M_PFPGA2SSDB_2_PPCIe lane 2 positive (FPGA-to-SSD2)
B37DP6_C2M_NFPGA2SSDB_2_NPCIe lane 2 negative (FPGA-to-SSD2)
B38GNDGNDGround✔️
B39GNDGNDGround✔️
B40RES0N/CPassed through✔️
C1GNDGNDGround✔️
C2DP0_C2M_PFPGA2SSDA_0_PPCIe lane 0 positive (FPGA-to-SSD1)
C3DP0_C2M_NFPGA2SSDA_0_NPCIe lane 0 negative (FPGA-to-SSD1)
C4GNDGNDGround✔️
C5GNDGNDGround✔️
C6DP0_M2C_PSSDA2FPGA_0_PPCIe lane 0 positive (SSD1-to-FPGA)
C7DP0_M2C_NSSDA2FPGA_0_NPCIe lane 0 negative (SSD1-to-FPGA)
C8GNDGNDGround✔️
C9GNDGNDGround✔️
C10LA06_PN/CPassed through✔️
C11LA06_NN/CPassed through✔️
C12GNDGNDGround✔️
C13GNDGNDGround✔️
C14LA10_PN/CPassed through✔️
C15LA10_NN/CPassed through✔️
C16GNDGNDGround✔️
C17GNDGNDGround✔️
C18LA14_PN/CPassed through✔️
C19LA14_NN/CPassed through✔️
C20GNDGNDGround✔️
C21GNDGNDGround✔️
C22LA18_P_CCN/CPassed through✔️
C23LA18_N_CCN/CPassed through✔️
C24GNDGNDGround✔️
C25GNDGNDGround✔️
C26LA27_PN/CPassed through✔️
C27LA27_NN/CPassed through✔️
C28GNDGNDGround✔️
C29GNDGNDGround✔️
C30SCLI2C_SCLI2C Clock✔️
C31SDAI2C_SDAI2C Data (bidirectional)✔️
C32GNDGNDGround✔️
C33GNDGNDGround✔️
C34GA0GA0EEPROM Address Bit 1 (A1)✔️
C3512P0V_112V012VDC✔️
C36GNDGNDGround✔️
C3712P0V_212V012VDC✔️
C38GNDGNDGround✔️
C393P3V_13V3Passed through✔️
C40GNDGNDGround✔️
D1PG_C2MPGPower Good (Driven by carrier)✔️
D2GNDGNDGround✔️
D3GNDGNDGround✔️
D4GBTCLK0_M2C_PREFCLKA_FPGA_P100MHz PCIe reference clock for the FPGA
D5GBTCLK0_M2C_NREFCLKA_FPGA_P100MHz PCIe reference clock for the FPGA
D6GNDGNDGround✔️
D7GNDGNDGround✔️
D8LA01_P_CCN/CPassed through✔️
D9LA01_N_CCN/CPassed through✔️
D10GNDGNDGround✔️
D11LA05_PN/CPassed through✔️
D12LA05_NN/CPassed through✔️
D13GNDGNDGround✔️
D14LA09_PN/CPassed through✔️
D15LA09_NN/CPassed through✔️
D16GNDGNDGround✔️
D17LA13_PN/CPassed through✔️
D18LA13_NN/CPassed through✔️
D19GNDGNDGround✔️
D20LA17_P_CCN/CPassed through✔️
D21LA17_N_CCN/CPassed through✔️
D22GNDGNDGround✔️
D23LA23_PN/CPassed through✔️
D24LA23_NN/CPassed through✔️
D25GNDGNDGround✔️
D26LA26_PN/CPassed through✔️
D27LA26_NN/CPassed through✔️
D28GNDGNDGround✔️
D29TCKN/CPassed through✔️
D30TDITDI-TDOPassed through✔️
D31TDOTDI-TDOPassed through✔️
D323P3VAUX3V3AUX3.3VDC Power supply for EEPROM✔️
D33TMSN/CPassed through✔️
D34TRST_LN/CPassed through✔️
D35GA1GA1EEPROM Address Bit 0 (A0)✔️
D363P3V_23V3Passed through✔️
D37GNDGNDGround✔️
D383P3V_33V3Passed through✔️
D39GNDGNDGround✔️
D403P3V_43V3Passed through✔️
E1GNDGNDGround✔️
E2HA01_P_CCN/CPassed through✔️
E3HA01_N_CCN/CPassed through✔️
E4GNDGNDGround✔️
E5GNDGNDGround✔️
E6HA05_PN/CPassed through✔️
E7HA05_PN/CPassed through✔️
E8GNDGNDGround✔️
E9HA09_PN/CPassed through✔️
E10HA09_PN/CPassed through✔️
E11GNDGNDGround✔️
E12HA13_PN/CPassed through✔️
E13HA13_PN/CPassed through✔️
E14GNDGNDGround✔️
E15HA16_PN/CPassed through✔️
E16HA16_PN/CPassed through✔️
E17GNDGNDGround✔️
E18HA20_PN/CPassed through✔️
E19HA20_PN/CPassed through✔️
E20GNDGNDGround✔️
E21HB03_PN/CPassed through✔️
E22HB03_PN/CPassed through✔️
E23GNDGNDGround✔️
E24HB05_PN/CPassed through✔️
E25HB05_PN/CPassed through✔️
E26GNDGNDGround✔️
E27HB09_PN/CPassed through✔️
E28HB09_PN/CPassed through✔️
E29GNDGNDGround✔️
E30HB13_PN/CPassed through✔️
E31HB13_PN/CPassed through✔️
E32GNDGNDGround✔️
E33HB19_PN/CPassed through✔️
E34HB19_PN/CPassed through✔️
E35GNDGNDGround✔️
E36HB21_PN/CPassed through✔️
E37HB21_PN/CPassed through✔️
E38GNDGNDGround✔️
E39VADJ_1N/CPassed through✔️
E40GNDGNDGround✔️
F1PG_M2CN/CPassed through✔️
F2GNDGNDGround✔️
F3GNDGNDGround✔️
F4HA00_P_CCN/CPassed through✔️
F5HA00_P_CCN/CPassed through✔️
F6GNDGNDGround✔️
F7HA04_PN/CPassed through✔️
F8HA04_PN/CPassed through✔️
F9GNDGNDGround✔️
F10HA08_PN/CPassed through✔️
F11HA08_PN/CPassed through✔️
F12GNDGNDGround✔️
F13HA12_PN/CPassed through✔️
F14HA12_PN/CPassed through✔️
F15GNDGNDGround✔️
F16HA15_PN/CPassed through✔️
F17HA15_PN/CPassed through✔️
F18GNDGNDGround✔️
F19HA19_PN/CPassed through✔️
F20HA19_PN/CPassed through✔️
F21GNDGNDGround✔️
F22HB02_PN/CPassed through✔️
F23HB02_PN/CPassed through✔️
F24GNDGNDGround✔️
F25HB04_PN/CPassed through✔️
F26HB04_PN/CPassed through✔️
F27GNDGNDGround✔️
F28HB08_PN/CPassed through✔️
F29HB08_PN/CPassed through✔️
F30GNDGNDGround✔️
F31HB12_PN/CPassed through✔️
F32HB12_PN/CPassed through✔️
F33GNDGNDGround✔️
F34HB16_PN/CPassed through✔️
F35HB16_PN/CPassed through✔️
F36GNDGNDGround✔️
F37HB20_PN/CPassed through✔️
F38HB20_PN/CPassed through✔️
F39GNDGNDGround✔️
F40VADJ_2N/CPassed through✔️
J1GNDGNDGround✔️
J2CLK3_BIDIR_PN/CPassed through✔️
J3CLK3_BIDIR_PN/CPassed through✔️
J4GNDGNDGround✔️
J5GNDGNDGround✔️
J6HA03_PN/CPassed through✔️
J7HA03_PN/CPassed through✔️
J8GNDGNDGround✔️
J9HA07_PN/CPassed through✔️
J10HA07_PN/CPassed through✔️
J11GNDGNDGround✔️
J12HA11_PN/CPassed through✔️
J13HA11_PN/CPassed through✔️
J14GNDGNDGround✔️
J15HA14_PN/CPassed through✔️
J16HA14_PN/CPassed through✔️
J17GNDGNDGround✔️
J18HA18_PN/CPassed through✔️
J19HA18_PN/CPassed through✔️
J20GNDGNDGround✔️
J21HA22_PN/CPassed through✔️
J22HA22_PN/CPassed through✔️
J23GNDGNDGround✔️
J24HB01_PN/CPassed through✔️
J25HB01_PN/CPassed through✔️
J26GNDGNDGround✔️
J27HB07_PN/CPassed through✔️
J28HB07_PN/CPassed through✔️
J29GNDGNDGround✔️
J30HB11_PN/CPassed through✔️
J31HB11_PN/CPassed through✔️
J32GNDGNDGround✔️
J33HB15_PN/CPassed through✔️
J34HB15_PN/CPassed through✔️
J35GNDGNDGround✔️
J36HB18_PN/CPassed through✔️
J37HB18_PN/CPassed through✔️
J38GNDGNDGround✔️
J39VIO_B_M2C_1N/CPassed through✔️
J40GNDGNDGround✔️
K1VREF_B_M2CN/CPassed through✔️
K2GNDGNDGround✔️
K3GNDGNDGround✔️
K4CLK2_BIDIR_PN/CPassed through✔️
K5CLK2_BIDIR_PN/CPassed through✔️
K6GNDGNDGround✔️
K7HA02_PN/CPassed through✔️
K8HA02_PN/CPassed through✔️
K9GNDGNDGround✔️
K10HA06_PN/CPassed through✔️
K11HA06_PN/CPassed through✔️
K12GNDGNDGround✔️
K13HA10_PN/CPassed through✔️
K14HA10_PN/CPassed through✔️
K15GNDGNDGround✔️
K16HA17_P_CCN/CPassed through✔️
K17HA17_P_CCN/CPassed through✔️
K18GNDGNDGround✔️
K19HA21_PN/CPassed through✔️
K20HA21_PN/CPassed through✔️
K21GNDGNDGround✔️
K22HA23_PN/CPassed through✔️
K23HA23_PN/CPassed through✔️
K24GNDGNDGround✔️
K25HB00_P_CCN/CPassed through✔️
K26HB00_P_CCN/CPassed through✔️
K27GNDGNDGround✔️
K28HB06_P_CCN/CPassed through✔️
K29HB06_P_CCN/CPassed through✔️
K30GNDGNDGround✔️
K31HB10_PN/CPassed through✔️
K32HB10_PN/CPassed through✔️
K33GNDGNDGround✔️
K34HB14_PN/CPassed through✔️
K35HB14_PN/CPassed through✔️
K36GNDGNDGround✔️
K37HB17_P_CCN/CPassed through✔️
K38HB17_P_CCN/CPassed through✔️
K39GNDGNDGround✔️
K40VIO_B_M2C_2N/CPassed through✔️
G1GNDGNDGround✔️
G2CLK1_M2C_PN/CPassed through✔️
G3CLK1_M2C_NN/CPassed through✔️
G4GNDGNDGround✔️
G5GNDGNDGround✔️
G6LA00_P_CCN/CPassed through✔️
G7LA00_N_CCN/CPassed through✔️
G8GNDGNDGround✔️
G9LA03_PN/CPassed through✔️
G10LA03_NN/CPassed through✔️
G11GNDGNDGround✔️
G12LA08_PN/CPassed through✔️
G13LA08_NN/CPassed through✔️
G14GNDGNDGround✔️
G15LA12_PN/CPassed through✔️
G16LA12_NN/CPassed through✔️
G17GNDGNDGround✔️
G18LA16_PN/CPassed through✔️
G19LA16_NN/CPassed through✔️
G20GNDGNDGround✔️
G21LA20_PN/CPassed through✔️
G22LA20_NN/CPassed through✔️
G23GNDGNDGround✔️
G24LA22_PN/CPassed through✔️
G25LA22_NN/CPassed through✔️
G26GNDGNDGround✔️
G27LA25_PN/CPassed through✔️
G28LA25_NN/CPassed through✔️
G29GNDGNDGround✔️
G30LA29_PN/CPassed through✔️
G31LA29_NN/CPassed through✔️
G32GNDGNDGround✔️
G33LA31_PN/CPassed through✔️
G34LA31_NN/CPassed through✔️
G35GNDGNDGround✔️
G36LA33_PN/CPassed through✔️
G37LA33_NN/CPassed through✔️
G38GNDGNDGround✔️
G39VADJ_3VADJPassed through✔️
G40GNDGNDGround✔️
H1VREF_A_M2CN/CPassed through✔️
H2PRSNT_M2C_LGNDGround✔️
H3GNDGNDGround✔️
H4CLK0_M2C_PN/CPassed through✔️
H5CLK0_M2C_NN/CPassed through✔️
H6GNDGNDGround✔️
H7LA02_PN/CPassed through✔️
H8LA02_NN/CPassed through✔️
H9GNDGNDGround✔️
H10LA04_PPERST_BPassed through✔️
H11LA04_NPEDET_BPassed through✔️
H12GNDGNDGround✔️
H13LA07_PN/CPassed through✔️
H14LA07_NN/CPassed through✔️
H15GNDGNDGround✔️
H16LA11_PN/CPassed through✔️
H17LA11_NN/CPassed through✔️
H18GNDGNDGround✔️
H19LA15_PN/CPassed through✔️
H20LA15_NN/CPassed through✔️
H21GNDGNDGround✔️
H22LA19_PN/CPassed through✔️
H23LA19_NN/CPassed through✔️
H24GNDGNDGround✔️
H25LA21_PN/CPassed through✔️
H26LA21_NN/CPassed through✔️
H27GNDGNDGround✔️
H28LA24_PN/CPassed through✔️
H29LA24_NN/CPassed through✔️
H30GNDGNDGround✔️
H31LA28_PN/CPassed through✔️
H32LA28_NN/CPassed through✔️
H33GNDGNDGround✔️
H34LA30_PN/CPassed through✔️
H35LA30_NN/CPassed through✔️
H36GNDGNDGround✔️
H37LA32_PN/CPassed through✔️
H38LA32_NN/CPassed through✔️
H39GNDGNDGround✔️
H40VADJ_4VADJPassed through✔️