Example Designs and How-to Videos

Example designs

Single SSD designs

Use the single SSD designs if you only intend on loading the FPGA Drive FMC with 1x SSD. The SSD should be connected to the first slot (SSD1).

Dual SSD designs

Use the dual SSD designs if you intend on loading the FPGA Drive FMC with 2x SSDs. The SSDs will connect to both slots SSD1 and SSD2.

Our Github repo contains example designs for these FPGA/MPSoC evaluation boards.

Target boardSingle SSD designDual SSD design
PicoZed FMC Carrier Card V2 with PicoZed 7015/30LPC: YesNot supported
KC705 Evaluation boardHPC: Yes
LPC: Yes
Not supported
KCU105 Evaluation boardHPC: Yes
LPC: Yes
HPC: Yes
LPC: Not supported
VC707 Evaluation boardHPC1: Yes
HPC2: Yes
Coming soon for HPC1 and HPC2
VC709 Evaluation boardHPC: YesComing soon
ZC706 Evaluation boardHPC: Yes
LPC: Yes
Not supported (Zynq-7000 devices only have 1x PCIe block)
ZCU106 Evaluation boardHPC0: Yes
HPC1: Yes
HPC0: Yes
HPC1: Not supported

Notes:

  1. If you are using the older version (Rev-B) of FPGA Drive FMC with only one M.2 connector, then you will only be able to use the single SSD designs.

How-to Videos

Hardware Installation Guide

Loopback Testing with IBERT

Part 1: Hardware setup

How to attach the M.2 loopback modules and prepare your hardware for the IBERT loopback test.

Part 2: Using IBERT in Vivado

Download the pre-built IBERT bitstreams here: https://opsero.com/downloads/fpgadrive/ibert. Try this: disable the DFE (decision feedback equalizer) when doing a 2D eye scan – the gigabit traces on the FPGA Drive FMC have very low losses, so the performance is generally better without the DFE.

Part 3: Generate your own IBERT

How to generate an IBERT bitstream for your own hardware if you can’t find a pre-built bitstream here.